module drive_division  
#(
	parameter data_bits = 32 //数据位宽
)
(  
	input clk,
	input en,
	
	input[data_bits - 1:0] dividend, //被除数  
	input[data_bits - 1:0] divisor,  //除数
  
	output reg [data_bits - 1:0] yshang,//商数  
	output reg [data_bits - 1:0] yyushu  //余数
);  
  
reg[data_bits - 1:0] tempa;  
reg[data_bits - 1:0] tempb;  
reg[2*data_bits - 1:0] temp_a;  
reg[2*data_bits - 1:0] temp_b;  
  
reg [5:0]i; 
reg [1:0] state;
localparam 
	state_begin			= 2'd0,
	state_second		= 2'd1,
	state_shif			= 2'd2,
	state_calculate 	= 2'd3;
	
always @(posedge clk)
	case(state)
			
		state_begin :begin
			if(en)
				begin  
					tempa <= dividend;  
					tempb <= divisor;
					state <= state_second;
				end  
		end
		
		state_second : begin
				temp_a <= {{data_bits{1'b0}},tempa}; 
				temp_b <= {tempb,{data_bits{1'b0}}}; 
				i <= 6'd0;
				state <= state_shif;
		end
		
		state_shif : begin
			temp_a <= {temp_a[2*data_bits - 2:0],1'b0};
			state <= state_calculate;
		end
		
		state_calculate : begin
			if(i >= data_bits) begin
				yshang <= temp_a[data_bits - 1:0];  
				yyushu <= temp_a[2*data_bits - 1:data_bits];
				state <= state_begin;					
			end
			else begin  
				i <= i + 1'b1;
				if(i >= data_bits - 1)
					state <= state;
				else
					state <= state_shif;
				if(temp_a[2*data_bits - 1:data_bits] >= tempb)  
					temp_a <= temp_a - temp_b + 1'b1;  
				else  
					temp_a <= temp_a;  
			end   
		end
		
		default : state <= state_begin;
	endcase
  
endmodule  